One of the last processes in the production of semiconductor integrated circuits (IC) is multi-leveled packaging, which includes expanding the electrode pitch of the IC chips containing the circuits for subsequent levels of packaging; protecting the chip from mechanical and environmental stress; providing proper thermal paths for channeling heat dissipated by the chip; and forming electronic interconnections. The manner in which the IC chips are packaged dictates the overall cost, performance, and reliability of the packaged chips, as well as of the system in which the package is applied.
Package types for IC chips can be broadly classified into two groups: hermetic-ceramic packages and plastic packages. A chip packaged in a hermetic package is isolated from the ambient environment by a vacuum-tight enclosure. The package is typically ceramic and is utilized in high-performance applications. A chip packaged in a plastic package, on the other hand, is not completely isolated from the ambient environment because the package is composed of an epoxy-based resin. Consequently, ambient air is able to penetrate the package and adversely affect the chip over time. Recent advances in plastic packaging, however, has expanded their application and performance capability. Plastic packages are cost-effective due to the fact that the production process is typically facilitated by automated batch-handling.
A recent development in the packaging of IC chips is the ball grid array (BGA) package, which may be utilized with either ceramic packages or plastic packages and involves different types of internal package structures. The BGA package uses multiple solder balls or bumps for electrical and mechanical interconnection of IC chips to other microelectronic devices. For example, a very large scale integration (VLSI) or an ultra large scale integration (ULSI) chip may be electrically connected to a circuit board or other next level packaging substrate using the solder balls or bumps. The BGA technique is included under a broader connection technology known as “Controlled Collapse Chip Connection-C4” or “flip-chip” technology.
As illustrated in FIG. 1, in BGA or “flip-chip” packaging technology, the IC chip substrate 1, which often contains millions of integrated circuits, is initially layered with a fixture or solder resist material 2, which may be a dry film photoresist (DFR) layer and which functions as a mold for subsequent formation of multiple solder bumps 4 on the chip substrate 1. The DFR layer 2 is typically about 120 μm thick, and multiple apertures 3, corresponding to the matrix array of solderable surfaces on the chip substrate 1, extend through the PR layer 2. Solder paste is then applied to the DFR layer 2 using a squeegee, and the solder paste fills the apertures 3. As the solder paste is subsequently reflowed by heating, the solder paste forms mushroom-shaped solder bumps 4 which attach to solder pads on the surface of the chip substrate 1. Finally, the DFR layer is removed, leaving the solder bumps 4 on the surface of the chip substrate 1 for connection of microelectronic devices thereto.
FIG. 2 illustrates a typical conventional system for removal of dry film photoresist (DFR) polymer material. The system 10 includes a process container 11, typically having an outer tank 12 connected in fluid communication with an inner tank 13. A container outlet conduit 15 leads from the inner tank 13 to a solvent re-claim tank 16, which is connected to a particle filter 18 by a tank outlet conduit 17. The particle filter 18 is capable of filtering particles of about 0.1 μm wide and larger. A filter outlet conduit 19 connects the particle filter 18 to a circulation pump 20, and a pump outlet conduit 21 connects the circulation pump 20 to the outer tank 12 of the process container 11.
FIG. 3 illustrates a typical process for removing the DFR polymer film 2 from the chip substrate 1 after formation of the solder bumps 4 thereon, using the system 10 of FIG. 2. After the chip substrate 1 is initially placed in the inner tank 13 of the process container 11, organic solvent normally contained in the outer tank 12 is allowed to flow into the inner tank 13. The chip substrate 1 is allowed to soak in the organic solvent for about 5-10 minutes, during which time DFR particles 6 begin to dislodge from the DFR layer 2 into the solvent. Finally, the chip substrate 1 is agitated in the inner tank 13, such as by use of sonic waves, and the remaining DFR particles 6 are dislodged from the chip substrate 1 and into the solvent. The chip substrate 1 is then removed from the inner tank 13, with the DFR layer 2 removed therefrom and the solder bumps 4 remaining thereon. The organic solvent is then drained from the outer tank 12 and into the solvent re-claim tank 16 and stored there until subsequent use of the solvent is required, at which time the solvent is distributed by operation of the circulation pump 20, through the particle filter 18 and back into the outer tank 12 of the process container 11.
As it flows from the outer tank 12, the solvent carries DFR particles having a variety of sizes to the solvent re-claim tank 16, and subsequently, to the particle filter 18, which effectively screens all particles having a size of typically about 0.1 μm and larger and prevents these particles from entering and clogging the circulation pump 20. However, many of the particles screened by the particle filter 18 have a size of about 1.5 mm to about 2.0 mm, and these larger particles tend to clog the particle filter 18 to such a degree as to render the particle filter 18 inoperative after about 2 hours of operation. Consequently, the particle filter 18 must be cleaned or replaced after about 2 hour segments of operation of the system 10, resulting in significant down-time for semiconductor chip processing.